1. Field of the Invention
The present invention relates to a logic circuit constructed with MIS FET's (Metal-Insulator-Semiconductor Field Effect Transistors) and, particularly, to a logic circuit whose power consumption is reduced.
2. Description of Related Art
In the recent design of a CMIS integrated circuit, attention is paid to a technique for reducing power consumption thereof. This tendency is related mainly to the heat generation problem due to recent increases in device operating speed and the popularization of mobile devices.
That is, when an operating frequency is increased due to an increase of the operating speed of the device, the frequency of switching is increased and, hence, the power consumption is increased, resulting in increased heat generation. The device generating a large amount of heat requires a heat radiating technique or a device cooling technique, causing manufacturing cost to be increased. Therefore, in order to reduce the device manufacturing cost and make such a radiator or cooling device unnecessary, the power consumption must be reduced.
On the other hand, the mobile device uses a battery as a power source. Therefore, the increase of power consumption leads to a reduction of the driving time of the battery. Therefore, in order to avoid a reduction of the drive time of the battery, the reduction of the power consumption is also necessary.
Under the circumstance, the necessity of a technique for reducing power consumption of a device is becoming more and more important.
Various methods for reducing power consumption have been proposed. Among them, a method for operating a device at a low voltage by reducing a source voltage is the most effective. However, when the source voltage is reduced, a new problem that a switching speed of a MIS FET is lowered occurs. Therefore, a method for reducing a source voltage without reducing the switching speed of the MIS FET by reducing an absolute value of a threshold value Vt of the MIS FET has been proposed. For a device having a source voltage of, for example, 5V, the absolute value of the threshold value Vt is about 0.7V. In order to prevent the switching speed of the MIS FET from being lowered when the source voltage is reduced to as low as 1.8V to 2.0V, the absolute value of the threshold value Vt is lowered to as low as 0.3V to 0.4V.
When the absolute value of the threshold value Vt is lowered, a leak current of the MIS FET during an OFF time thereof is increased, causing the power consumption of the logic circuit constructed with MIS FET's to be increased. Therefore, the effect of reduction of power consumption obtained by reducing the source voltage can not be utilized effectively.
In order to solve this problem, Japanese Patent Application Laid-open Nos. Hei 6-21443 and Hei 9-55470 propose techniques in which the leak current when the MIS FET is in OFF state is reduced by controlling a substrate potential of the MIS FET during a time period in which a logic circuit constructed with MIS FET's is in inactive state, that is, during an idle time. According to the disclosed techniques, the leak current of the logic circuit in the idle time can be reduced. However, in a time period in which the logic circuit is in active state, that is, the logic circuit is operating, there is completely no reduction of power consumption since the leak current continuously flows. Consequently, the total reduction effect of power consumption is low and, particularly, in a case where the inactive state time is short, the reduction of power consumption is very low.